Technical Field
The present invention relates to vertical field effect transistors and, more particularly, to gate formation in a vertical field effect transistor using selective atomic layer deposition.
Description of the Related Art
Forming metal gates in vertical field effect transistors (FETs), where the source and drain regions are vertically aligned and have a vertical channel between them, is challenging. In particular, existing recess processes are subject to a severe loading effect, which causes non-uniform metal deposition heights between regions of the FETs. Loading effect is the dependence of an etch process on the size of the area to etch or recess, with the result being that a larger area has a higher etch rate. This makes it difficult to align the top surface of the gate layer with the tops of the channel structures. In particular, for metal gate vertical FETs, the gate is formed by a deposition-recess process, with the gate length being the thickness of the metal gate after the recess. The loading effect can cause an uneven thickness in the metal gate, leading to a non-uniform gate length. In such a case, the uneven metal gates need to be recessed to make them even with one another before fabrication can continue.